I. Field
The present invention relates generally to electronics circuits, and more specifically to a direct digital synthesizer (DDS).
II. Background
In a modem communication device, multiple clock signals with frequencies that are unrelated may be needed for various functions. For example, a clock signal with a first frequency may be needed for a digital signal processing subsystem, another clock signal with a second frequency may be needed for a sampled analog subsystem, and so on.
Multiple clock signals with unrelated frequencies may be generated in various manners. In one conventional design, a clock generator with a single phase locked loop (PLL) is operated at a high frequency. The clock signal from this generator is divided in frequency by different integer values to obtain multiple output clock signals with different frequencies. This design places stringent requirements on the PLL in terms of performance and power consumption. In another conventional design, a separate PLL is provided for each subsystem requiring a clock signal with a different frequency. This design is undesirable because multiple PLLs for multiple clock signals normally consume a large amount of power and occupy a large area.
In yet another conventional design, an MN counter is used to divide an input clock signal (e.g., from a PLL) by a divider value to obtain an output clock signal with the desired frequency. The divider value is a ratio of two integer values M and N (i.e., N/M), where M<2·N for proper operation of the MN counter and N/M may be an integer or non-integer value. If the N/M divider value is not an integer, which is often the case, then the desired frequency is obtained by dividing the input clock signal in frequency by └N/M┘ for some of the time and by ┌N/M┐ for the remainder of the time, where └x┘ is a floor operator that provides the nearest lower integer value for x and ┌x┐ is a ceiling operator that provides the nearest higher integer value for x. This division with two integer values of └N/M┘ and ┌N/M┐ results in the output clock signal having inherent jitter that can be as large as one period of the input clock signal. For example, if the input clock frequency is 100 MHz, then the worst-case jitter for the output clock signal from the MN counter is 10 nsec.
Various methods for reducing jitter in the output clock signal from an MN counter have been proposed. For example, some methods reduce jitter by estimating the amount of phase shift needed in each output clock cycle to eliminate the jitter and then adjusting the output clock phase accordingly. In any case, most of these methods rely on absolute (voltage and/or current) reference levels to perform the phase shift estimation and/or adjustment and are thus prone to performance degradation due to circuit component mismatches and integrated circuit (IC) process variations.
There is therefore a need in the art for techniques to generate a clock signal having less jitter.